1. Field of the Invention
The present invention relates to an ESD protection circuit and, more particularly, to a protection circuit for a transfer gate circuit connected to a power supply or a GND level.
2. Description of the Related Art
ESD (electrostatic damage) protection circuits of this type have been used to protect an internal circuit from ESD as described in, for example, Japanese patent Application Laid-Open No. 2-1954.
FIG. 1 illustrates an embodiment of circuitry of a conventional ESD protection circuit. Referring to FIG. 1, the drains of a p-type MOS transistor 11 and an n-type MOS transistor 12 as protection devices are connected to a line connecting an external terminal 10 and an internal circuit 8. The source and gate of the p-type MOS transistor 11 are both connected to a power supply potential VDD 2 and the source and gate of the n-type MOS transistor 12 are both connected to a ground potential GND 3 to form diodes, respectively. The internal circuit 8 has an internal circuit 82 with a p-type MOS transistor 821 and an n-type MOS transistor 822 which are connected to the external terminal 10 and a transfer gate circuit 81 with a p-type MOS transistor 811L and an n-type MOS transistor 812.
An external ground potential GND terminal 1 has a protection circuit consisting of a p-type MOS transistor 4 and an n-type MOS transistor 5. The drains of the transistors 4 and 5 are connected to a line connecting the external terminal 1 and the internal circuit 8. The source and gate of the p-type MOS transistor 4 are both connected to a power supply potential VDD and the source and gate of the n-type MOS transistor 5 are both connected to a ground potential GND to form diodes, respectively.
The p-type MOS transistor 11 has a structure wherein its well is open to prevent any current from flowing into the power supply VDD of the internal circuit 8 from the drain of the p-type MOS transistor 11 through the well even when static electricity at a high positive voltage is applied to the external terminal 10.
Further, when it is desired to disable a circuit such as a flip-flop which receives an input signal at the transfer gate circuit 81, the input of the transfer gate circuit 81 has been switched by a master slice 13 such that it is disconnected from an output signal of the internal circuit 82 and is directly connect to an external ground potential GND) terminal 1 having protection circuits consisting or the p-type MOS transistor 4 and the p-type MOS transistor 5.
According to the conventional technique shown in FIG. 1, however, since static electricity at a high voltage is directly applied to the drains of the p-type and n-type MOS transistors 821, 822 of the internal circuit 82, there is a problem in that ESD occurs when the transfer gate 81 of the internal gate is switched by the master slice 13 to the external ground potential GND.